Monday, September 14, 2026

Saturday, September 05, 2026

design in 2 weeks

https://x.com/semidoped/status/2094838495512563880

CMU 15-213 — Introduction to Computer Systems

This is an unusually good foundation for this job. It covers machine code, performance evaluation/optimization, computer arithmetic, memory organization, networking and concurrency.

CMU 15-213 course materials

If you don't already have a strong systems background, I would do this before diving deeply into SoCs.

Then:

CMU 15-740 — Computer Architecture

This is much closer to the actual Meta position. CMU describes it as a deep treatment of modern computer-system design, with particular emphasis on parallel systems and hardware/software interaction.

CMU 15-740 Computer Architecture

And if you become really serious:

CMU 18-742 — Computer Architecture and Systems

This is the research-level version: state-of-the-art architecture, architecture research, and a semester research project.

You do not need the PhD course to prepare for the job, though. 15-740 is the sweet spot.

Hennessy & Patterson — Computer Architecture: A Quantitative Approach

This is probably the one book I'd buy/read for this job.

The important word is quantitative.

You're not merely learning:

"A cache is faster than DRAM."

You're learning to ask:

"How much faster?"
"Under what workload?"
"What happens when 8 agents contend for the memory system?"
"How much bandwidth do we actually need?"
"Is the bottleneck computation, latency, bandwidth, or interconnect?"

That's exactly the mindset of the job.

. Then learn memory systems very deeply

This job specifically says:

SoC architecture, NoCs, memory subsystem, QoS

I'd spend an enormous amount of time here.

You want to be comfortable with:

CPU/accelerator → cache → LLC → memory controller → DRAM

and understand:

latency
bandwidth
cache misses
locality
outstanding requests
memory-level parallelism
bank conflicts
row-buffer behavior
scheduling
contention
arbitration
QoS
fairness
starvation
tail latency
MIT's computer architecture material is a good accessible starting point; its memory-hierarchy material explicitly frames memory as a pipeline bottleneck and explains the hierarchy used to alleviate it.

5. Learn the Roofline model

This is one of the first performance-analysis concepts I'd make second nature.

The fundamental question is:

Is my workload compute-bound or memory-bound?

The Roofline model expresses this through arithmetic intensity:

operations / bytes moved

Low arithmetic intensity → memory bandwidth becomes the ceiling.

High arithmetic intensity → compute throughput becomes the ceiling.

NVIDIA has a very good practical explanation, including hierarchical Roofline analysis that lets you reason about different levels of the memory hierarchy.

NVIDIA Roofline performance analysis

This is worth learning by actually measuring programs, not just reading about it.

6. The most important thing you could build

Wednesday, September 02, 2026

Jalapeno

https://www.siliconcodesign.com/p/an-advanced-system-architecture-breakdown

https://x.com/jasonschips/status/2095084434185924625 - Hot chips 2026

https://x.com/QQ_Timmy/status/2095128760542790121 - Google training and inference

Monday, August 31, 2026

The Quest for Community: A Study in the Ethics of Order and Freedom

using category theory for middle income trap

https://x.com/EsmeLKPartridge/status/2094368404018725218

Tuesday, August 04, 2026

Graph engineering

Stay tuned for English version book --- https://x.com/leafmeta/status/2083768641145938336

A graph contains not only what to do but also what is known. Furthermore, the latter is a much older concept—the lineage leading from knowledge graphs to ontology and the semantic web. Therefore, this book divides graph engineering into two tracks.

Knowledge Graph Engineering Track 1: What the Model Knows; Ontology, Schema, Source; Time, Quality, Verification.

Agent Graph Engineering Track 2: What the Model Does; State, Reducer, Superstep; Tools, Authority, Termination Conditions. Both are built with nodes and edges.

Friday, July 24, 2026

Conjecture COnjecture everywhere

Conjecture about recurring digits in Pre Algebra homework

Wednesday, July 22, 2026

polynomial multiplication

polynomial multiplication · point-value swap · roots of unity · recursion · one flipped sign

prompt like a mathematician

Tuesday, July 21, 2026

Claude agents

Build with Thariq

a model trained on short tasks generalizes to problems 100x longer for free

Monday, July 20, 2026

Slack monitor

Slack probe

Here is how on-chip controllers monitor and react to degrading timing slack in real time.

1. In-Situ Slack Monitors

Instead of measuring voltage or temperature as proxies, controllers use dedicated hardware sensors embedded directly inside the critical logic paths.

Canary Circuits: Replica logic paths that mimic the slowest paths on the chip but are intentionally designed to fail slightly earlier than the actual operational logic. [1]
Razor Flip-Flops: Specialized latches that sample data twice—once at the normal clock edge and a second time slightly later. If the two samples disagree, it indicates the timing slack has shrunk to a dangerous level.
Transition Detectors: Sensors that watch data lines during a "guardband" window right before the clock edge. Any signal transition inside this window triggers a warning that slack is critically low.

2. Controller-Driven Recovery Mitigation

When the on-chip telemetry controller detects that the timing slack is nearing zero, it executes rapid hardware-level interventions:

[Slack Warning Triggered] │ ├──► 1. Clock Throttling (Immediate): Stretches or skips next clock cycle to grant more time. ├──► 2. Voltage Boosting (Transient): Signals PMIC to raise Vdd to speed up transistors. └──► 3. Architectural Re-execution: Re-runs the cycle securely if a Razor flip-flop detects a late transition.

Dynamic Frequency Scaling (DFS): The controller immediately reduces the clock frequency (stretching the cycle time) to artificially open up the timing slack.
Adaptive Voltage Scaling (AVS): The controller commands the Power Management IC (PMIC) to step up the voltage, forcing the transistors to switch faster and restoring the timing margin.
Instruction Re-execution: If a Razor flip-flop catches a late-arriving signal that missed the primary clock edge, the controller stalls the pipeline and replays the instruction using the correct, late-sampled data.

Predictive Failure Analysis

Controllers also log the frequency of these near-miss slack events. If a specific core or execution unit continuously triggers slack warnings under normal workloads, the controller flags it as aging or degraded (due to phenomena like Negative-Bias Temperature Instability, or NBTI). The system firmware can then permanently map out or down-clock that specific block to avoid permanent SDC risks.

TRANSPOSING INFORMATION USING SHADOW LATCHES AND ACTIVE LATCHES FOR EFFICIENT DIE AREA IN PROCESSING SYSTEM

Sunday, July 19, 2026

SSD

How to write to SSD

REO: Revisiting Erase Operation for Improving Lifetime and Performance of Modern NAND Flash-Based SSDs

Wednesday, July 15, 2026

negotiating in pajamas

why you should learn RL by touching nothing but the config and watching the curve go up, and why the intelligence ceiling of a specialised open-source model now subsumes the frontier for most real tasks

systemdesign concepts

Mathematical foundations of generative AI

llm compressing language

Sunday, July 05, 2026

Understanding and Answering

https://paulabartabajo.substack.com/p/how-to-pass-a-technical-interview

Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification

Agentic AI-based Coverage Closure for Formal Verification

NY story

After a red eye flight, our five year old was tired. We were meeting friends in the new york city during the layover of international travel.

When the city was just waking up on a holiday, our friend bought us breakfast from a food stand.As we were leaving with our food, the stand owner gave our toddler a donut. He refused money for it. Intended to make the kid happy but it made a strong impression on us. A welcome to the city!!

I have been to the city many times hauling back a suticase full of second hand books from The Strand Store, Times square visit that I rendered in a poem, but that donut!!

10 years later

Any parent with a kid needs to know, where the restrooms are!! Our fiend dropped us at an entrance. There were few levels in the building. The receptionist said that the closest restroom was at a place called Occ.. something.

We started running, from one way pointer to another. It was a miracle that so much running could be done with a full bladder. Finally, the apple store pointer helped. Later in the evening, we were being shown around the Occulus, which we had seen 10 years ago, and as we were walking through it, our eyes fell on the Apple store sign and my younger one and I gave out a big laugh of the place etched in our minds, coming full circle in many ways.