Session 23 AI accelerators ISSCC 2025
https://fpga.org/2014/12/31/the-past-and-future-of-fpga-soft-processors/
Sunday, February 22, 2026
PIM GPT
Friday, February 20, 2026
Tuesday, February 17, 2026
Compute Conference
mode collapse and mode dropping.
SIMD yield from disciplining the programmer into writing branchless functions and pipelines - good thread
SWAR SIMD-within-a-Register Arithmetic
real gap between hyperscale GPU scheduling (frontier clusters) and the everyday reality of small research labs running long single-GPU jobs.
Short answer:
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overlaps with GPU context preemption, memory oversubscription, and gang scheduling, but today’s systems don’t expose a clean, transparent “pause/resume GPU job” abstraction.
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There is research on this — just scattered across OS, ML systems, and datacenter scheduling literature rather than in one clean textbook chapter.
Let’s unpack it.
1. Is the Idea Plausible?
Conceptually, yes — but with sharp edges.
Its combining:
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GPU page tables
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NVIDIA Unified Virtual Memory (UVM)
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NVIDIA Multi-Process Service (MPS)
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Host-side suspension of the CPU process
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Demand paging back to device memory
In theory, this gives you:
Coarse-grained GPU job preemption (tens of seconds)
via memory eviction + host suspension
The key insight is important:
You don’t need millisecond-level SM preemption.
You need coarse-grained fairness and priority enforcement.
That’s much more tractable.
2. Why This Is Hard in Practice
The core problems:
(A) GPU Context Isn’t Just Memory
Even if memory can be paged:
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Kernel state
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In-flight work
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Streams
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CUDA graphs
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Allocator metadata
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Device-side malloc
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cuDNN/cuBLAS internal workspaces
These aren’t always safely “freeze-dried.”
GPU drivers do support context switching, but:
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It’s optimized for graphics + short compute kernels
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Not for long-running ML training loops
(B) Page Thrashing Would Be Brutal
UVM paging over PCIe:
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~12–32 GB/s (PCIe)
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~900 GB/s (HBM)
So paging device memory to host is ~30–70× slower bandwidth.
If a low-priority job pages back in 40 GB of model state, you’ve just paid a huge penalty.
But — if switching is infrequent and intentional (tens of seconds), this may be acceptable.
This becomes a policy problem:
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When to evict?
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When to preserve?
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When to checkpoint instead?
(C) GPUs Are Built for Throughput, Not Preemptibility
CPU OSes evolved around:
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Fast context switch
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Full memory virtualization
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Demand paging as first-class
GPUs evolved around:
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Huge batches
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Massive parallel throughput
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Long kernels
Preemption was not the primary design goal.
3. This Is an Active Research Area
The idea intersects with several areas:
1️⃣ GPU Preemption Research
Look for work on:
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Fine-grained GPU preemption
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Kernel slicing
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Thread block level preemption
Search terms:
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"GPU kernel preemption"
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"GPU context switching overhead"
Many papers out of systems conferences (OSDI, SOSP, ASPLOS).
2️⃣ Cluster-Level GPU Scheduling
A lot of this appears in ML systems research:
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USENIX OSDI papers
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ACM SOSP / ASPLOS
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USENIX ATC
Look at systems like:
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Gandiva (time-slicing DL training jobs)
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Tiresias (GPU cluster scheduling)
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Salus (fine-grained GPU sharing for DL)
These explicitly try to solve:
Short job first scheduling for GPUs
They often:
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Time-slice at iteration boundaries
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Require framework integration (e.g., PyTorch hooks)
Which is exactly what you’re trying to avoid.
3️⃣ OS Textbooks That Cover Foundations
No mainstream OS textbook deeply covers GPU preemption yet, but these are foundational:
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Operating Systems: Three Easy Pieces
(Best conceptual grounding in scheduling + memory) -
Modern Operating Systems
(Classic coverage of preemption + VM)
For GPU-specific material:
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“Heterogeneous Computing” courses (advanced grad level)
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Papers from ASPLOS / ISCA / MICRO
4. The Deep Insight
The strongest idea expressed is this:
Coarse-grained, memory-driven GPU job suspension is “good enough.”
That’s actually a very practical engineering perspective.
You don’t need:
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Fine-grained SM warp preemption
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Transparent kernel-level swapping
You need:
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“Pause at iteration boundary”
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Evict memory
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Resume later
Which suggests a hybrid model:
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Driver-level memory eviction
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Framework-level safe points
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Scheduler-level policy
5. What Would Make This Realistic?
If I were designing this for a modest research cluster:
Practical Path:
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Force iteration-boundary synchronization
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Inject scheduler checks in training loops
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Use CUDA context destruction + memory release
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Reload from checkpoint
That’s ugly — but stable.
memory-based freeze/resume could work if:
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GPU driver exposed explicit "evict context"
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CUDA allocator was virtualized via shim (as you suggest with MPS)
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Frameworks cooperated minimally
But today, that’s not officially supported.
6. Why NVIDIA Doesn’t Prioritize This
Nvidia would prefer you to Just Buy More GPUs!
There’s some truth there — but also:
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Hyperscalers want multi-tenant utilization
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Research clusters are a smaller market
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Preemption reduces peak throughput
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Hardware simplicity favors non-preemptive design
That said, with GPU scarcity cycles, this problem becomes more important.
7. If You Want to Dive Deeper
Search for:
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“Gang scheduling for GPUs”
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“Preemptible deep learning jobs”
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“GPU memory oversubscription”
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“Time-slicing deep learning workloads”
Look up papers like:
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Gandiva (Microsoft Research)
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Salus
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Tiresias
Most are conference papers, not textbooks.
8. My Take
idea is:
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Technically informed
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Feels feasible at coarse granularity
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Underexplored for small clusters
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Very aligned with real pain points in academia
The hardest part isn’t paging.
It’s defining:
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Safe preemption boundaries
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Consistent device state
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Allocator determinism
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Avoiding pathological thrashing
But as a research direction? Completely legitimate.
If you’d like, I can:
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Sketch what a “minimal viable preemptible GPU runtime” would look like
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Or point you to specific seminal papers in this area
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Or evaluate whether this could be a publishable systems paper idea
This is exactly the kind of idea that turns into a good ASPLOS paper.
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