Systolic Arrays

 Google systolic arrays

Systolic Architectures and other classes

Microsoft systolic arrays on sparse data

Parallel and real time computation

Not square Cornami systolic arrays

VLSI Resources

 ASIC books and resources

28nm STA

 28nm STA using PBA and GBA

Understanding 28-nm SoC Design With ARM-Based Cores

   Flexible Abstract model to decrease the size of netlist.

Implementation challenges for large 28nm socs

Global clock channel could limit reroute of deisgn

Memory-to-flop paths have high logic levels and a memory delay of ~400ps. 

create placement regions near the memories to ensure less buffering in the path, and achieve timing closure.

Clock gating issues also cause high congestion in the localized area.

different placement rules for different types of standard cells/macros, local power drop targets on top of the global targets, special clock tree design to take care of the skew and to minimize the number of buffers on clock tree. 

clock tree synthesis for low power

"Optimal grouping clock tree sinks for clock gating during both the RTL design and synthesis stages offer significant advantages for power saving. The grouping and clock gating that can be coded manually by the RTL designer who knows the architecture and typical application scenarios for the device is the most critical part that contributes most to the power savings. "

At a block level, you also have them all on or off at once with a selection for it. 

CHOPPER AND CHOPPER-STABILISED AMPLIFIERS, WHAT ARE THEY ALL ABOUT THEN?

 Chopper and chopper stabilised amplifiers

Bablle Hypothesis

 

Hey all, bad news! Two papers confirming your worst intuitions about leadership:
🗣Babble Hypothesis: Whoever speaks the most is likely to be made leader, regardless of what they say
🤷‍♂️Peter Principle: People are promoted out of roles they are good at & into ones they are bad at! pic.twitter.com/zPAYO2BhWy

— Ethan Mollick (@emollick) February 10, 2021

Do you think you could do every new field that you study or like?

 The Burden of Capability

Capability trap

Low node technology and power

 What is the CTL output for DFT?

Integrated Power Management, Leakage Control and Process Compensation Technology for Advanced Processes aka what are FF, SS corners.

Why SF and FS are skewed corners? (slide 10)

Multi corner multi mode analysis

Process Corner explosion

Power challenges at 10nm and below [“At that time the dynamic power could mainly be taken care of with I/Os, memories, and clocks. If you did something good in those areas, it was fine and you did what you could in order to get it under control. That’s changing, and the logic component (the data path logic and control logic) is becoming a pretty significant portion of the total dynamic power within the chip. "]

Design rule violatio fixing in timing closure

Testing analog circuits becoming more difficult

Performance Robustness Analysis of VLSI Circuits with Process Variations Based on Kharitonov Theorem

16 plant theorem for windmills