Toastmaster speeches

1. The Ice Breaker  - Practise, Practise, Practise

2. Organize Your Speech –speech format of a fixed point 1 point2. Leave some flexibility in the points supporting the main points.

3. Get to the Point – Time your speech as you say it aloud. This will help you weed out sentences that don’t fit in your speech and timeframe.

4. How to Say It – Make it a part of daily life, so it becomes natural over time.

5. Your Body Speaks – Kindra Hall

6. Vocal Variety – Mimic the energy of other speakers on the radio and TV. Get comfortable listening to your voice. Find ‘Voice memos’ app on your smart phone and listen to your self speaking.

7. Research Your Topic -

8. Get Comfortable with Visual Aids – Pecha Kucha

9. Persuade with Power – Conduct an auction.

10. Inspire Your Audience – Share what you were born to share with the world.

Career Development

Putting common career advice to the test 

Track what excites you or scare you

What metrics mean something

Know what options are available – Networking, Books, Other organization knowledge, Public figures

Which do you see yourself in? Make a future resume. Keep refining it.

Do you know your obstacles? – Feedback

What are the new skills needed to your final destination? – Experience, Education- formal course, online course, Books, Data (eg Strategy, risk as opportunity), Dealing with Complexity, Modeling a situation, Your learning style and growth through challenging with other styles.

Your support team – Find a Mentor, Keep family in the ring, Sustaining motivation and going back to the beginning if this is not the right path.

Giving it back – Mentoring

Pushing ourselves to find the limit

Plaza with different opportunities. There are many steps. Do you want to take one path and reach the pinnacle or go up a bit on the others, which could mean having to climb new stairs and going down a few. Or find lateral bridges.

Know your users needs 

Analog

 

http://www.electropages.com/2017/08/texas-instruments-mcus-supported-extensive-ecosystem-reference-designs-code-examples/

Low Power

http://www.eetimes.com/document.asp?doc_id=1332131

http://www.ti.com/lit/an/scha004/scha004.pdf

http://www.linear.com/products/Voltage_Output_DACs

https://electronics.stackexchange.com/questions/28628/why-dont-microcontrollers-generally-have-on-chip-dacs

current-output DACs

http://www.analog.com/media/en/training-seminars/tutorials/MT-019.pdf

I2C/SPI interface to external DAC

https://www.maximintegrated.com/en/app-notes/index.mvp/id/3439

https://books.google.com/books?id=CB9GaAU1dwsC&pg=PA323&lpg=PA323&dq=pic+dacs&source=bl&ots=Hia7z5wybf&sig=jcu-4YYO7K09dnobm__T7C-atdg&hl=en&sa=X&ved=0ahUKEwjt05PosMrVAhVhHGMKHaPNAP8Q6AEIZzAJ#v=onepage&q=pic%20dacs&f=false

Skills and Achievements

 

Developed

 

Structured

 

Implemented

 

Solved

 

Monitored

How do you innovate?

How do you motivate?

How are you working on a shared vision that sets the long term goals for the organization, for the team.

PM skills

Conflict resolution

Negotiation

Decision-making

How do you present?

How do you coach?

Adaptability

Flexibility

Fungibility

 

More VLSI links

 how good must a voltage reference be

https://www.analog.com/media/en/training-seminars/tutorials/MT-019.pdf

Crossing clock boundaries

http://www.ece.utep.edu/courses/web5375/Notes_files/ee5375_asynch.pdf

https://www.eetimes.com/understanding-clock-domain-crossing-issues/#

https://ieeexplore.ieee.org/document/6942125

http://www.eememes.com/2017/07/digitally-assisted-analog-circuits.html

https://www.edn.com/building-a-low-power-hold-friendly-scan-chain/

skew analysis

https://pages.hmc.edu/harris/research/tau99slides.pdf

CCD and not focusing on skew since local more dominant

https://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-8-CTS.pdf

Clock tree design for robust low power design

http://www.ispd.cc/slides/2006/8-1.pdf

International Symposium on Physical Design

http://www.ispd.cc/?page=archives

https://users.ece.utexas.edu/~mcdermot/

Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM

http://users.ece.utexas.edu/~mcdermot/vlsi1/main/lectures/lecture_9.pdf

3 Strategies for Holding Yourself Accountable

 3 strategies for holding yourself accountable

More verilog design

ESNUG 

1. design a soda vending machine

Vending Machine verilog design

2. What is RFFE (MIPI standard)

3. What is clk insertion delay? (Clock tree balancing)

4. generate div by 2, div by 3 and div by 4 clock - state machine showing counter design

5. First  there is a register 

    I want to latch the output only with another pulse as an enable

    Now with a config bit as a mux sel want both 1 and 2 .

   Mux cannot be after the flop or latch as it will glitch

(I put mux on data input and clk input for the first register, wondering how to tap two different outputs - one after the first reg and two after the second latch without  amux to select. Answer is to put the mux for data (output of first reg which will be input for the second case of latching, the other input is original d, so instead of using first reg for plain output, we now use second latch for it)and mux for clock (pulse or original clk)

This seems very close to pg 46 Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog - Figure 33 - Sample ASIC & FPGA synchronizer cell for synthesis and simulation

6. On the same chip if clock is delayed between two sections how do you ensure the data is still captured fine as there is a ck-q delay and the clock might have shifted by that much. Use the data on the opposite edge of the clock than the launching one.

7. How do you sync fast to slow clk domain and vice a versa

8. Will duty cycle uncertainty matter if the design is one edge based only?

9. Are clock and its generated clock timed?

10. What is latency?

Perl for FSM