Multi core

 Meta-ai-custom-silicon-olivia-wu

"As we work on the next generations of MTIA chips, we’re constantly looking at bottlenecks in the system, such as memory and communication across different chips so that we can put together a well-balanced solution to scale and future-proof our silicon."

Constructure Computer architecture

Computer Architecture Carnegie Mellon

Multi core architecture

. AI Hardware Design (Memory & Interconnect Focus)

📚 Key Readings

1. Efficient Processing of Deep Neural Networks — by Sze, Chen, Yang, and Emer

   • IEEE Access Paper

   • Covers memory bottlenecks, reuse strategies, and on-chip dataflows in DNN accelerators.

   • 🔥 Highly cited and foundational.

2. Google TPU Architecture Whitepapers

   • TPU v1: Google TPU v1

   • TPU v2/v3: Google TPU v2 & v3

   • Focuses on systolic arrays, memory bandwidth trade-offs, and system balance.

3. Meta’s MTIA Architecture Overview

   • next-generation-meta-training-inference-accelerator-AI-MTIA
     

   • Discusses how Meta balances compute and memory, and bottleneck analysis behind their chip design.

4. NVIDIA Hopper or Ampere Architecture Deep Dives

   • Whitepapers cover NVLink, sparsity handling, HBM integration.

   • Example: Hopper Whitepaper (PDF)

5. IEEE MICRO – Special Issues on DNN Accelerators

   • Look for 2018–2022 issues for real-world chip case studies from companies like Cerebras, Graphcore, Google, NVIDIA, etc.

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🎓 Video Courses & Talks

1. MIT 6.S897: Machine Learning Hardware

   • Playlist: YouTube Link

   • Includes full lectures on memory architectures, dataflow mapping, and interconnect design.

2. Stanford CS316: Advanced Chip Design for ML

   • Covers real-world ML accelerator design, power/memory trade-offs.

   • YouTube Course Archive

3. Hot Chips Conference Talks (YouTube)

   • Look up Hot Chips 2020–2024.

   • Especially: Cerebras, Tesla Dojo, NVIDIA Hopper, Meta MTIA, Graphcore.

4. UC Berkeley CS250 / CS152

   • CS250: VLSI Systems Design

   • Covers chip organization, memory hierarchies, and physical interconnects.

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🧩 B. Chiplet Packaging & Interconnect (Scalability & Bandwidth Focus)

📚 Key Readings

1. AMD Chiplet Design Whitepapers

   • Learn about Infinity Fabric and 3D V-Cache.

   • Example overview

2. Intel Foveros and EMIB Packaging

   • Intel architecture journals or tech briefings on EMIB/Foveros

3. TSMC SoIC and CoWoS Technology Briefs

   • Focused on chip stacking, TSVs, and advanced packaging.

4. IEEE ISSCC / VLSI Symposium Proceedings

   • Industry-standard conferences for chiplet and interconnect technologies.

   • Look for papers from AMD, Intel, TSMC, Apple.

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🎓 Talks, Courses, and Resources

1. Chiplet Summit Talks (YouTube)

   • Covers real-world modular silicon architectures and interconnect protocols.

   • Example Playlist

2. IEEE Hot Interconnects Conference

   • Annual conference focusing on the future of interconnect and silicon systems.

3. Open Compute Project (OCP) – Chiplet and Interconnect Working Group

   • OCP Chiplet Standardization

4. OpenROAD Project – Physical Design Automation for Chiplets

   • Website

   • Learn about automated packaging and interconnect-aware floorplanning.