More verilog design

ESNUG 

1. design a soda vending machine

Vending Machine verilog design

2. What is RFFE (MIPI standard)

3. What is clk insertion delay? (Clock tree balancing)

4. generate div by 2, div by 3 and div by 4 clock - state machine showing counter design

5. First  there is a register 

    I want to latch the output only with another pulse as an enable

    Now with a config bit as a mux sel want both 1 and 2 .

   Mux cannot be after the flop or latch as it will glitch

(I put mux on data input and clk input for the first register, wondering how to tap two different outputs - one after the first reg and two after the second latch without  amux to select. Answer is to put the mux for data (output of first reg which will be input for the second case of latching, the other input is original d, so instead of using first reg for plain output, we now use second latch for it)and mux for clock (pulse or original clk)

This seems very close to pg 46 Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog - Figure 33 - Sample ASIC & FPGA synchronizer cell for synthesis and simulation

6. On the same chip if clock is delayed between two sections how do you ensure the data is still captured fine as there is a ck-q delay and the clock might have shifted by that much. Use the data on the opposite edge of the clock than the launching one.

7. How do you sync fast to slow clk domain and vice a versa

8. Will duty cycle uncertainty matter if the design is one edge based only?

9. Are clock and its generated clock timed?

10. What is latency?

Perl for FSM