Verilog Design

 Learning Perl

• Implementation of Asynchronous FIFO design -   in detail
• Basics on timing, power, Power variations w.r.t PVT parameters
• Logic design question - Inputs A[1:0], B[1:0] comes as serial data i.e; A[0], A[1], B[0], B[1]. A start pulse (one cycle long) is driven to indicate that that input data is valid when A[0] is available on serial data input. Control and data paths to implement an adder that adds A, B and gives the output on a serail bus as S[0], S[1], Cout 
• testbench considerations for verifying DDR controller (every transaction with the DDR controller happens via crossbar)

• clock domain crossing - how to synchronize- various methods Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog

gray to binary

binary to grey

Parameterized gray-code counter SystemVerilog model

• Glitch free clock mux implementation  Techniques to make clock switching glitch free