Saturday, October 30, 2021

Logic Design Engineer

 QAT (Quick Assist Technology) hardware design team enables Data Center Technology thru a set of scalable hardware accelerators, like lossless compression, network security like secure key establishment, IPSec, SSL/TLS, and firewall and data center virtualization technology.

QAT team, e CPM (Content Processing Module) front end design team, where you will work on RTL/DFX development and integration activities within the Custom Logic
Responsibilities will include, but are not limited to:

  • Perform logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.

  • Participate in the development of Architecture and Microarchitecture specifications for the Logic components.

  • Provide IP integration support to SoC customers and represents RTL team.

  • Implement RTL in System Verilog, validating the design, synthesizing the design, and closing timing.

  • High-level Architecture through to the details of timing.

  • Work with specifications at multiple levels, including the HAS and MAS (microarchitecture spec).

  • Balance design trade-offs with modularity, scalability, DFX requirements, power, area, and performance.


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