Understanding 28-nm SoC Design With ARM-Based Cores
Flexible Abstract model to decrease the size of netlist.
Implementation challenges for large 28nm socs
Global clock channel could limit reroute of deisgn
Memory-to-flop paths have high logic levels and a memory delay of ~400ps.
create placement regions near the memories to ensure less buffering in the path, and achieve timing closure.
Clock gating issues also cause high congestion in the localized area.
different placement rules for different types of standard cells/macros, local power drop targets on top of the global targets, special clock tree design to take care of the skew and to minimize the number of buffers on clock tree.
clock tree synthesis for low power
"Optimal grouping clock tree sinks for clock gating during both the RTL design and synthesis stages offer significant advantages for power saving. The grouping and clock gating that can be coded manually by the RTL designer who knows the architecture and typical application scenarios for the device is the most critical part that contributes most to the power savings. "
At a block level, you also have them all on or off at once with a selection for it.
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