lower latency, faster access, less delay, lower power
“Typically, CPUs are optimized for capacity,
while accelerators and GPUs are optimized for bandwidth.
However, with the exponentially growing model sizes, we see constant demand for both capacity and bandwidth without tradeoffs. We are seeing more memory tiering, which includes support for software-visible HBM plus DDR, and software transparent caching that uses HBM as a DDR-backed cache. Beyond CPUs and GPUs, HBM is also popular for data center FPGAs.”
"GDDR is a very power-hungry interface, but HBM is a super power-efficient interface. "
"Arm has developed memory system resource partitioning and monitoring ( MPAM ) framework to tie resource controls to the software that accesses the memory system."
DVFS and AVFS
. “If you miss that (usecase), then you’re planning for some other chip,” Mijatovic said.
a set of the most common use cases to optimize the data lines,
to optimize the place-and-route.
"every power domain costs wiring and isolation cells."
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