lower latency, faster access, less delay, lower power
“Typically, CPUs are optimized for capacity,
while accelerators and GPUs are optimized for bandwidth.
However, with the exponentially growing model sizes, we see constant demand for both capacity and bandwidth without tradeoffs. We are seeing more memory tiering, which includes support for software-visible HBM plus DDR, and software transparent caching that uses HBM as a DDR-backed cache. Beyond CPUs and GPUs, HBM is also popular for data center FPGAs.”
"GDDR is a very power-hungry interface, but HBM is a super power-efficient interface. "
"Arm has developed memory system resource partitioning and monitoring ( MPAM ) framework to tie resource controls to the software that accesses the memory system."
DVFS and AVFS
. “If you miss that (usecase), then you’re planning for some other chip,” Mijatovic said.
a set of the most common use cases to optimize the data lines,
to optimize the place-and-route.
"every power domain costs wiring and isolation cells."
QAT (Quick Assist Technology) hardware design team enables Data Center Technology thru a set of scalable hardware accelerators, like lossless compression, network security like secure key establishment, IPSec, SSL/TLS, and firewall and data center virtualization technology.
QAT team, e CPM (Content Processing Module) front end design team, where you will work on RTL/DFX development and integration activities within the Custom Logic
Responsibilities will include, but are not limited to:
Perform logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.
Participate in the development of Architecture and Microarchitecture specifications for the Logic components.
Provide IP integration support to SoC customers and represents RTL team.
Implement RTL in System Verilog, validating the design, synthesizing the design, and closing timing.
High-level Architecture through to the details of timing.
Work with specifications at multiple levels, including the HAS and MAS (microarchitecture spec).
Balance design trade-offs with modularity, scalability, DFX requirements, power, area, and performance.
Systolic Architectures and other classes
Microsoft systolic arrays on sparse data
Understanding 28-nm SoC Design With ARM-Based Cores
Flexible Abstract model to decrease the size of netlist.
Implementation challenges for large 28nm socs
Global clock channel could limit reroute of deisgn
Memory-to-flop paths have high logic levels and a memory delay of ~400ps.
create placement regions near the memories to ensure less buffering in the path, and achieve timing closure.
Clock gating issues also cause high congestion in the localized area.
different placement rules for different types of standard cells/macros, local power drop targets on top of the global targets, special clock tree design to take care of the skew and to minimize the number of buffers on clock tree.
clock tree synthesis for low power
"Optimal grouping clock tree sinks for clock gating during both the RTL design and synthesis stages offer significant advantages for power saving. The grouping and clock gating that can be coded manually by the RTL designer who knows the architecture and typical application scenarios for the device is the most critical part that contributes most to the power savings. "
At a block level, you also have them all on or off at once with a selection for it.
Hey all, bad news! Two papers confirming your worst intuitions about leadership:
— Ethan Mollick (@emollick) February 10, 2021
🗣Babble Hypothesis: Whoever speaks the most is likely to be made leader, regardless of what they say
🤷♂️Peter Principle: People are promoted out of roles they are good at & into ones they are bad at! pic.twitter.com/zPAYO2BhWy
What is the CTL output for DFT?
Integrated Power Management, Leakage Control and Process Compensation Technology for Advanced Processes aka what are FF, SS corners.
Why SF and FS are skewed corners? (slide 10)
Multi corner multi mode analysis
Power challenges at 10nm and below [“At that time the dynamic power could mainly be taken care of with I/Os, memories, and clocks. If you did something good in those areas, it was fine and you did what you could in order to get it under control. That’s changing, and the logic component (the data path logic and control logic) is becoming a pretty significant portion of the total dynamic power within the chip. "]
Design rule violatio fixing in timing closure
Testing analog circuits becoming more difficult
Performance Robustness Analysis of VLSI Circuits with Process Variations Based on Kharitonov Theorem
Synthesizable Delay Line architecture
CDC clock domain crossing
So: for current to flow in a circuit, it has to flow from someplace and to someplace. In the case of this USB signal, it needs to flow back to ground. I used a ground pour on both sides to try to accomplish that. Unfortunately with only two layers, they're not very contiguous. 3/ pic.twitter.com/4sNOKy28Rn
— joey 🏳️🌈 castillo (@josecastillo) July 18, 2021
JEE main Maths Definite integrals previous year questions with solutions
The Limit of a Riemann Sum (aka definite integral) saves the day pic.twitter.com/Q4gS7JpDHK
— DℝOℕ∈ (@d_r_o_n_e) September 19, 2019
Students had questions about graphs. This graph lesson cleared up fundamentals. They even wanted to learn more about step function. This picture of miles and cost as in the taxi meter made it easier for kids to understand. Then just to make it more relevant, I asked if the taxi driver should adopt y=2 or y=x or y=x power 2 or step function. Which would net him more money?
We talked a little bit about the floor and ceiling functions too.
After the above graphs primer, kids were ready for the graph problems in
